Thermal management is a critical bottleneck to the performance and reliability of microelectronic circuits and systems. The situation worsens as the sizes of the microelectronic systems reduce and their power consumption increases due to added functionality. Wide-bandgap GaN and SiC devices operate at much higher power densities compared to Si and GaAs devices and also generate more heat. In addition, the trend for dimensional scaling and 3D integration for size and weight reduction creates a very challenging environment for all microelectronic systems. For example, 3D integration and multi-layer stacking compound the problem by embedding heat generating power amplifiers (PAs) inside a multi-layer stack surrounded by high thermal resistance layers separated from a heat sink.
Further, GaN technology, especially large-scale phased arrays of GaN devices, requires addressing the heat management problem while still maintaining ease of access to the devices for low RF loss and reduced parasitics. GaN devices produce heat fluxes in excess of 1 kW/cm2, which are difficult to dissipate using existing cooling technologies. Conventional assembly methods rely on mounting GaN MMIC on metallic heat sinks, which may be Cu, CuW, and other suitable heat sinks, and utilizing thermal interface materials (TIMs), such as silver epoxy and AuSn solder. Such TIMs have low thermal conductivities which become a bottleneck in cooling GaN devices and can cause serious reliability problems due to the potential existence of air voids.
Next generation RF front-ends for EW, Radar and communication systems will incorporate GaN circuits for power, linearity and robustness in both the receiver and transmitter paths and CMOS and/or SiGe components for signal processing and beamforming. This combination of components in dense packaging requires improved thermal management.
U.S. patent application Ser. No. 13/306,827, filed Nov. 29, 2011 describes a method for packaging, assembling and cooling GaN and other types of integrated circuits (ICs) by forming a free-standing electroformed heat sink within which all the components may be embedded. One method described in U.S. patent application Ser. No. 13/306,827 is shown in FIG. 1, which is further discussed below. The resulting assembly shown in step 4 of FIG. 1 is called an Integrated Thermal Array Plate (ITAP).
There are problems that occur in the making of an ITAP. Integrated circuits (ICs) may not be uniformly mounted on the carrier substrate, and the active faces of the ICs may not be protected during mounting. The embodiments of the present disclosure answer these and other needs.